This invention relates to a method and apparatus for analog-to-digital conversion. More particularly, the invention relates to a high accuracy, high speed, low power analog-to-digital conversion method and circuit.
The importance of high accuracy and speed, as well as low power consumption in an analog-to-digital converter ("ADC") is well known. This need is especially great in CMOS circuitry, where it is desirable to integrate ADC circuits with digital circuits on the same substrate. While some efforts have been made to integrate ADC circuits with digital circuits on the same CMOS substrate, the technology thus far has had serious drawbacks. Flash ADCs, discussed below, have been used to achieve high speed digital-to-analog conversion on a CMOS digital substrate, but suffer from mismatch errors, among other things. Pipeline ADC's, wherein high speed is achieved by using multiple segmented stages require linear capacitors that are difficult and expensive to realize.
There are several basic approaches to analog-to-digital conversion, and many variations thereof. One approach, known as charge integration conversion, works by sampling the analog signal, charging a capacitor with the sample, then discharging the capacitor at a known rate while counting the time it takes to discharge. The time is proportional to the sampled voltage. This approach is disclosed in LeChevalier U.S. Pat. No. 4,998,109 ("LeChevalier") and Kogan U.S. Pat. No. 5,298,902. A more sophisticated variation of this approach, known as dual-slope conversion, charges a capacitor for a known, controlled period of time before discharging the capacitor at a constant rate. Examples of this approach are disclosed in Hopkins U.S. Pat. No. 5,614,902; Liao U.S. Pat. No. 5,592,168; and George et al. U.S. Pat. No. Re. 34,428. While these methods can be very accurate, they are also relatively slow because the average time required is proportional to the number of levels the converter must resolve.
Another approach, similar to the charge integration approach, works by comparing a sample of the input signal to a reference signal whose amplitude varies with time in a known way, typically a ramp with a constant slope, and counting the time until the level of the reference signal is substantially equal to the level of the sample. That time is proportional to the level of the sample. Examples of this approach are disclosed in Cuthbert et al. U.S. Pat. No. 3,737,897 and Mallinson et al. U.S. Pat. No. 5,321,404. Like the charge integration approach, this "slope comparison" approach can produce very accurate results but is relatively slow. In addition, this approach has the drawback that it is susceptible to drift with temperature variations which change the manner in which the reference signal varies with time, such as by changing the slope of a ramp reference.
High speed analog-to-digital conversion can generally be achieved by an approach known as flash conversion. In this approach a plurality of comparators simultaneously compare the analog signal to each of the voltage levels to be resolved. This approach is described in LeChevalier. Some drawbacks of flash conversion are that it requires a large number of comparators which are expensive and increasingly impractical with increasing resolution, and that one analog signal drives many comparators, so expensive buffering is required to provide the necessary power.
A compromise on speed can be achieved using a successive approximation approach. In this approach, the analog signal is sampled and the sample is compared sequentially to successively closer values using a single comparator. An example of successive approximation is disclosed in Van Auken et al. U.S. Pat. No. 5,638,072. Successive approximation requires less circuitry and is faster than charge integration for the same resolution, but is much slower than flash conversion.
It would be desirable to employ an analog-to-digital conversion approach that achieves accuracy comparable to charge integration, without the drift problem of slope comparison, and achieves speed comparable to flash conversion.
In addition, all of the known approaches to digital-to-analog conversion employ comparators, which have inherent offset that introduces error. It would be desirable to substantially eliminate that error with minimal additional circuitry, particularly for integration with CMOS digital technology.
Accordingly, there is a need for a high accuracy, high speed, low power analog-to-digital conversion method and circuit.